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250 ksps, 6 - channel, simultaneous sampling, bipolar 16 - bit adc data sheet ad7656a features 6 independent analog - to - digital converters ( adcs ) true bipolar analog inputs pin - /software - selectable ranges: 10 v or 5 v fast throughput rate: 250 ksps i cmos ? process technology low power: 140 mw at 250 ksps with 5 v supplies wide input bandwi dth 86.5 db snr at 50 khz input frequency on - chip reference and reference buffers parallel, serial, and daisy - chain interface modes high speed serial interface serial peripheral interface (spi) /qspi?/ microwire ? /dsp compatible power - down mode: 100 mw maximu m 64- lead lqfp improved power supply sequencing ( pss ) robu stness applications power line monitoring systems instrumentation and control systems multi - axis positioning systems functional block dia gram v ss dgnd v dd ref convst a convst b convst c output drivers output drivers output drivers output drivers control logic buf buf buf agnd t/h t/h t/h t/h t/h t/h clk osc av cc dv cc v1 v2 v3 v4 v5 v6 ser/ p ar/se l cs v drive stby db8/dout a db9/dout b db10/dout c sclk rd wr/ref en/dis data/ control lines 11127-001 ad7656a 16-bit sar 16-bit sar 16-bit sar 16-bit sar 16-bit sar 16-bit sar figure 1. general descri ption the ad7656a 1 contain s six 16 - bit, fast, low power, successive approximation analog - to - digital converters ( adcs ) all in the one package that is designed on the i cmos ? process (industrial cmo s). i cmos is a process combining high voltage silicon with submicron cmos and complementary bipolar technologies . it enables the development of a wide range of high performance analog ics, capable of 33 v operation in a footprint that no previous generatio n of high voltage devices could achieve. unlike analog ics using conventional cmos processes, i cmos components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. the ad7656a features throughput rates of up to 250 ksps. it contain s wide bandwidth ( 12 mhz ) , track - and - hold amplifiers that can handle input frequencies up to 12 mhz. the conversion process and data acq uisition are controlled using convst x signals and an internal oscillator. three convst x pins (convst a, convst b, and convst c) allow independent, simultaneous sampling of the three adc pairs. the ad7656a has a high speed parallel and serial interface , allowing the device to interface with microprocessors or digital s ignal processors ( dsps ) . in serial interface mode, the ad7656a has a da isy - chain feature that allows multiple adcs to connect to a single serial interface. the ad7656a can accommodate true bipolar input signals in the 4 v ref range and 2 v ref range. the ad7656a also contains an on - chip 2.5 v reference. multifunction pin names may be referenced by their relevant function only. product highlights 1. six 16 - bit, 250 ksps adcs on board. 2. six true bipolar, high impedance analog inputs. 3. parallel and high speed serial interfaces. 1 protected by u.s. patent no. 6,731,232. rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for it s use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog device s. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
ad7656a data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 power supply sequencing ........................................................... 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ........................................... 10 terminology .................................................................................... 13 theory of operation ...................................................................... 15 converter details ....................................................................... 15 adc transfer function ............................................................. 16 reference section ....................................................................... 16 typical connection diagram ................................................... 16 driving the analog inputs ........................................................ 17 interface section ......................................................................... 17 software selection of adcs ...................................................... 19 serial read operation ................................................................ 21 daisy-c hain mode (dcen = 1, ser/ par /sel = 1) ............. 21 application hints ........................................................................... 24 layout .......................................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 12/ 13 rev ision 0: initial version rev. 0 | page 2 of 28
data sheet ad7656a specifications v ref = 2.5 v internal/ex ternal, av cc = 4.75 v to 5.25 v, dv cc = 4.75 v to 5.25 v, and v drive = 2.7 v to 5.25 v . for the 4 v ref range , v dd = 11 v to 16.5 v, and v ss = ?11 v to ?16.5 v . for the 2 v ref range , v dd = 6 v to 16.5 v , and v ss = ?6 v to ?16.5 v . f sample = 250 ksps, and t a = t min to t max , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal -to - noise + distortion (sinad) 1 84 85.5 db signal -to - noise ra tio (snr) 1 85 86.5 db total harmonic distortion (thd) 1 ? 90 db r ange pin = 0 ?92 db v dd /v ss = 6 v to 11 v r ange pin = 1 ?100 db v dd /v ss = 12 v to 16.5 v peak harmonic or spurious noise (sfdr) 1 ? 100 db intermodulation distortion (imd) 1 fa = 50 khz, fb = 49 khz second - order terms ?112 db third - order terms ? 107 db aperture delay 10 ns aperture delay matching 4 ns aperture jitter 35 ps channel - to - channel isolation 1 ? 100 db f in on unselected channels up to 100 khz full power bandwidth 12 mhz at ?3 db 2 mhz at ?0.1 db dc accuracy resolution 16 bits no missing codes 15 bits 16 bits at 25c integr al nonlinearity 1 3 lsb 1 lsb positive full - scale error 1 0.22% 0.75 % fs r positive full - scale error matching 1 0.35 % fs r bipolar zero - scale error 1 0.004% 0.023 % fs r bipolar zero - scale error matching 1 0.038 % fs r negative full - scale error 1 0.22% 0.75 % fs r negative full - scale error matching 1 0.35 % fs r analog input see table 6 for the min imum v dd /v ss for each range input voltage ranges ?4 v ref +4 v ref v range pin = 0 ?2 v ref +2 v ref v range pin = 1 dc leakage current 1 a input capacitance 2 10 pf 4 v ref range when in track mode 14 pf 2 v ref range when in track mode reference input/output reference in put voltage range 2.5 3 v dc leakage current 1 a input capacitance 2 18.5 pf ref en/ dis = 1 3 reference output voltage 2.49 2.51 v long - term stability 150 ppm 1000 hou rs reference temperature coefficient 25 ppm/c 6 ppm/c rev. 0 | page 3 of 28
ad7656a data sheet parameter min typ max unit test conditions/comments logic inputs input high voltage (v inh ) 0.7 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in ) 1 a typically 10 na, v in = 0 v or v drive input capac itance (c in ) 2 10 pf logic outputs output high voltage (v oh ) v drive ? 0.2 v i source = 200 a output low voltage (v ol ) 0.2 v i sink = 200 a floating state leakage current 1 a floa ting state output capacitance 2 10 pf output coding conversion rate conversion time 3.1 s track - and - hold acquisition time 1 , 2 550 ns throughput rate 250 ksps parallel interface mode only power requirements v dd range 6 16.5 v for the 4 v ref range, v dd = 11 v to 16.5 v v ss range ?6 ?16.5 v for the 4 v ref range, v ss = ?11 v to ?16.5 v av cc 4.75 5.25 v dv cc 4.75 5.25 v v drive 2.7 5 .25 v i total 4 digital inputs = 0 v or v drive normal mode (static) 28 ma av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v normal mode (operational) 26 ma f sample = 250 ksps, av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v i ss (operational) 0.25 ma v ss = ?16.5 v, f sample = 250 ksps i dd (operational) 0.25 ma v dd = 16.5 v, f sample = 250 ksps partial po wer - down mode 7 ma av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v full power - down mode ( stby pin) 80 ma sclk on or off, av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v power dissipation av cc = dv cc = v drive = 5.25 v, v dd = 16.5 v, v ss = ?16.5 v normal mode (static) 143 mw normal mode (operational) 140 mw f sample = 250 ksps partial power - down mode 35 mw full power - down mode ( stby pin) 100 mw 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 multifunction pin names m ay be referenced by their relevant function only. 4 includes i av cc , i v dd , i v ss , i v drive , and i dv cc . rev. 0 | page 4 of 28
data sheet ad7656a timing spec ifications av cc and dv cc = 4.75 v to 5.25 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v internal /external, t a = t min to t max , unless otherwise noted. for the 4 v ref range, v dd = 11 v to 16.5 v, and v ss = ?11 v to ?16.5 v , and f or the 2 v ref range , v dd = 6 v to 16.5 v, and v ss = ?6 v to ?16.5 v . sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. table 2 . paramete r limit at t min, t max unit description 1 v drive < 4.75 v v drive = 4.75 v to 5.25 v parallel interface mode t conv ert 3 3 s typ conversion time, internal clock t quiet 150 150 ns min minimum quiet time required between bus relinquish and start of next conversion t acq 550 550 ns min acquisition time t 1 60 60 ns min convst x high to busy high t 10 25 25 ns min minimum convst x low pulse t wake - up 2 2 ms max stby rising edge to convst x rising edge, not shown in figures 25 25 s max partial power - down mode parallel write operation t 11 15 15 ns min wr pulse width t 12 0 0 ns min cs to wr setup time t 13 5 5 ns min cs to wr hold time t 14 5 5 ns min data setup time before wr rising edge t 15 5 5 ns min data hold after wr rising edge parallel read operation t 2 0 0 ns min busy to rd delay t 3 0 0 ns min cs to rd setup time t 4 0 0 ns min cs to rd hold time t 5 45 36 ns min rd pulse width t 6 45 36 ns max data access time after rd falling edge t 7 10 10 ns mi n data hold time after rd rising edge t 8 12 12 ns max bus relinquish time after rd rising edge t 9 6 6 ns min minimum time between reads serial interface mode f sclk 18 18 mhz max frequency of serial read clock t 1 6 12 12 ns max delay from cs until sdata three - state disabled t 17 2 22 22 ns max data access time after sclk rising edge/ cs falling edge t 18 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 19 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 20 10 10 ns min sclk to data valid hold time after sclk falling edge t 21 18 18 ns max cs rising edge to sdata high impedance 1 multifunction pin names may be referenced by their relevant function only. 2 a buffer i s used on the data output pins for this measurement. 200a i ol 200a i oh 1.6v t o output pin c l 25pf 11127-002 figure 2 . load circuit for digit al output timing specification s rev. 0 | page 5 of 28
ad7656a data sheet absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v dd to agnd, dgnd 0 v to +16.5 v v ss to agnd, dgnd 0 v to ? 16.5 v v dd to av cc a v cc + 0.7 v to 16.5 v av cc to agnd, dgnd ? 0.3 v to +7 v dv cc to av cc ?0.3 v to av cc + 0.3 v dv cc to dgnd, agnd ?0.3 v to +7 v agnd to dgnd ?0.3 v to +0.3 v v drive to dgnd ?0.3 v to dv cc + 0.3 v analog input voltage to agnd v ss + 1 v to v dd ? 1 v digital input voltage to dgnd ?0. 3 v to v drive + 0.3 v digital output voltage to d gnd ?0.3 v to v drive + 0.3 v refin /refout to agnd ?0.3 v to av cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c pb/s n temperature, soldering reflow (10 sec to 30 sec) 240( 0)c pb - free temperature, soldering reflow 260(0)c 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolut e maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power supply sequenc ing simultaneous application of v dd and v ss is necessary to guarantee reliability of the device . in the case s where simultaneous appli cation cannot be guaranteed , v dd must power up before v ss . when a negative voltage is applied to the analog inputs before v dd and v ss are fully powered up , a 560 ? resistor must be placed on the analog inputs. a number of sequencing combinations can lead to temporary h igh current states; however, when all supplies are powered up, the device return s to normal operating currents . the analog input ( a in ) coming before av cc causes temporary high current on the analog inputs. d igital inputs before dv cc , and dv cc before other supplies , also cause temporary high current states. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4 - layer board. table 4 . thermal resistance package type ja jc unit 64 - lead lqfp 45 11 c/w esd caution rev. 0 | page 6 of 28
data sheet ad7656a pin configuration an d function descripti ons 64 db15 63 wr/ref en/dis 62 h/s se l 61 ser/ p ar/se l 60 a v cc 59 agnd 58 refcapc 57 agnd 56 refcapb 55 agnd 54 refca p a 53 agnd 52 agnd 51 refin/refout 50 a v cc 49 agnd 47 a v cc 46 a v cc 45 v5 42 v4 43 agnd 44 agnd 48 v6 41 a v cc 40 a v cc 39 v3 37 agnd 36 v2 35 a v cc 34 a v cc 33 v1 38 agnd 2 db13 3 db12 4 db 1 1 7 db8/dout a 6 db9/dout b 5 db10/dout c 1 db14/refbuf en/dis 8 dgnd 9 v drive 10 db7/hben/dcen 12 db5/dcin a 13 db4/dcin b 14 db3/dcin c 15 db2/se l c 16 db1/se l b 1 1 db6/sclk 17 db0/se l a 18 bus y 19 cs 20 rd 21 convst c 22 convst b 23 convst a 24 stb y 25 dgnd 26 dv cc 27 range 28 reset 29 w/b 30 v ss 31 v dd 32 agnd pin 1 ad7656a top view (not to scale) 11127-003 figure 3. pin configuration table 5 . pin function descriptions 1 pin no. mnemonic description 1 db14/refbuf en /dis data bit 14/ reference buffer enable and disable . when ser/ par / sel = 0, this pin acts as a three - state digital input/ output pin. 2, 3, 64 db13, db12, db15 data bit 1 3 , data bit 1 2 , and data bit 15. when ser/ p ar / sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, these pins are used to output the conversion result. when cs and wr are low, th ese pins are used to write to the control register. when ser/ par / sel = 1, tie these pins to dgnd. 4 db11 data bit 11/digital ground. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. whe n ser/ par / sel = 1, tie this pin to dgnd. 5 db10/dout c data bit 10/serial data output c. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1 and sel c = 1, this pin takes on its dout c function and outputs serial conversion data. this pin configures the serial interface to have three dout x output lines. 6 db9/dout b data bit 9/serial data output b. when ser/ par / sel = 0, pin 6 acts as a three - state parallel digital output pin. when ser/ par / sel = 1 and sel b = 1, pin 6 takes on its dout b function and outputs serial conversion data. this pin configures the serial interface to have two dout x output lines. 7 db8/dout a data bit 8/serial data output a. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1 and sel a = 1, this pin takes on its dout a function and outputs serial conversion data. 8, 25 dgnd digital ground. th ese pin s are the ground reference point for all digital circuitry on the ad7656a . connect b oth dgnd pins to the dgnd plane of a system. i deally, t he dgnd and ag nd voltages are at the same potential and must not be more than 0.3 v apart, even on a transient basis. 9 v drive logic power supply input. the voltage supplied at this pin determines the operating voltage of the interface. nominally , it is at the same sup ply as the supply of the host interface. decouple t his pin to dgnd, and place 10 f and 100 nf decoupling capacitors on the v drive pin. rev. 0 | page 7 of 28
ad7656a data sheet pin no. mnemonic description 10 db7/hben/dcen data bit 7/high byte enable/daisy - chain enable. when operating in parallel word mode (ser/ par / sel = 0 and w /b = 0), pin 10 takes on its data bit 7 function. when operating in parallel byte mode (ser/ par / sel = 0 and w /b = 1), pin 10 takes on its hben function. when in this mode and the hben pin is logic high, the data is output msb byte first on db15 to db 8. when the hben pin is logic low, the data is output lsb byte first on db15 to db 8. when operating in serial mode (ser/ par / sel = 1), pin 10 takes on its dcen function . when the dcen pin is logic high, the ad7656a operate s in daisy - chain mode with db5 to db 3 taking on their dcin a to dcin c function. when operating in serial mode but not in daisy - chain mode, ti e dcen to dgnd. 11 db6/sclk data bit 6/serial clock. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1, this pin takes on its sclk input function; it is the read ser ial clock for the serial transfer. 12 db5/dcin a data bit 5/daisy - chain input a. when ser/ par / sel is low, this pin acts as a three - state parallel digital output pin. when ser/ par sel = 1 and dcen = 1, this pin acts as d aisy - chain input a. when operating in serial mode but not in daisy - chain mode, tie this pin to dgnd. 13 db4/dcin b data bit 4/daisy - chain input b. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser / par / sel = 1 and dcen = 1, this pin acts as daisy - chain input b. when operating in serial mode but not in daisy - chain mode, tie this pin to dgnd. 14 db3/dcin c data bit 3/daisy - chain input c. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1 and dcen = 1, this pin acts as daisy - chain input c. when operating in serial mode but not in daisy - chain mode, tie this pin to dgnd. 15 db2/sel c data bit 2/sele ct dout c. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1, this pin takes on its sel c function; it is used to configure the serial interface. if this pin is 1, the serial interface operates with three dout output pins and enables dout c as a serial output. if this pin is 0, the dout c is not enabled to operate as a serial data output pin. leave u nused serial dout pins unconnected. 16 db1/sel b data bit 1/select dou t b. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1, this pin takes on its sel b function; it is used to configure the serial interface . if this pin is 1, the seria l interface operates with two or three dout x output pins and enables dout b as a serial output. if this pin is 0, the dout b is not enabled to operate as a serial data output pin and only one dout output pin, dout a, is used. leave u nused serial dout pins unconnected. 17 db0/sel a data bit 0/select dout a. when ser/ par / sel = 0, this pin acts as a three - state parallel digital output pin. when ser/ par / sel = 1, pin 17 takes on its sel a function; it is used to configure t he serial interface. if this pin is 1, the serial interface operates with one , two , or three dout x output pins and enables dout a as a serial output. when operating in serial mode, this pin must always be 1. 18 busy b usy output. this pin transitions hig h when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. do not initiate a new conversion on the ad7656a when the busy signal is high. 19 cs chip select. this active low logic input frames the data transfer. when both cs and rd are logic low in parallel mode, the output bus is enabled and the conversion r esult is output on the parallel data bus lines. when both cs and wr are logic low in parallel mode, db15 to db 8 are used to write data to the on - chip control register. in serial mode, the cs is used to frame the serial read transfer and clock out the msb of the serial output data. 20 rd read data. when both cs and rd are logic low in parallel mode, the output bus is enabled. in serial mode, hold the rd line low. 21, 22, 23 convst c, convst b , convst a conversion start input c , conversion start input b, and conversion start input a . these logic inputs are used to initiate conversions on the adc pairs. convst a is used to initiate si multaneous conversions on v1 and v2 , convst b is used to initiate simultaneous conversions on v3 and v4 , and convst c is used to initiate simultaneous conversions on v5 and v6. when convst x switches from low to high, the track - and - hold switch on the selec ted adc pair switches from track to hold , and the conversion is initiated. these inputs can also be used to place the adc pairs into partial power - down mode. 24 stby standby mode input. this pin is used to put all six on - chip adcs into standby mode. the stby pin is high for normal operation and low for standby operation. 26 dv cc digital power, 4.75 v to 5.25 v. ideally, t he dv cc and av cc voltages are at the same potential and must not be more than 0.3 v apart, even on a transient basis. decouple t his supply to dgnd, and place 10 f and 100 nf decoupling capacitors on the dv cc pin. rev. 0 | page 8 of 28
data sheet ad7656a pin no. mnemonic description 27 range analog input range selection. logic input. the logic level on this pin determines the input range of the analog input channels. whe n this pin is logic 1 at the falling edge of busy, the range for the next conversion is 2 v ref . when this pin is logic 0 at the falling edge of busy, the range for the next conversion is 4 v ref . in hardware select mode, the range pin is checked on th e falling edge of busy. in software mode ( h /s sel = 1), the range pin can be tied to dgnd , and the input range is determined by the rnga, rngb, and rngc bits in the control register. 28 reset reset input. when set to logic high, this pi n resets the ad7656a , and t he current conversion, if any, is aborted. the internal register is set to all 0s. in hardware mode, the ad765 6a is configured depending on the logic levels on the hardware select pins. in all modes, after power - up, the device must receive a reset pulse. the reset high pulse is typically 100 ns wide. after the reset pulse, the ad7656a needs to see a valid convst pulse to initiate a conversion; this typically consists of a high - to - low convst edge followed by a low -to - high convst edge. during the reset pulse, t he convst x signal must be high. 29 w /b word /byte input. when this pin is logic low, data can be transferred to and from the ad7656a using the parallel data lines db15 to db 0. when this pin is logic high, b yte mode is enabled. in this mode, data is transferred using data lines db15 to db 8 and db7 takes on its hben function. to obtain the 16- bit conversion result, 2 - byte reads are required. in serial mode, tie this pin to dgnd. 30 v ss negative power supply v oltage. this is the negative supply voltage for the analog input section . place 10 f and 100 nf decoupling capacitors on the v ss pin. 31 v dd positive power supply voltage. this is the positive supply voltage for the analog input section . place 10 f and 100 nf decoupling capacitors on the v dd pin. 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 agnd analog ground. ground reference point for all analog circuitry on the ad7656a . refer a ll analog input signals and any external reference signal to th e agnd voltage. connect a ll agnd pins to the agnd plane of a system. ideally, t he agnd and dgnd voltages are at the same potential and must not be more than 0.3 v apart, even on a transient basis. 33, 36, 39, 42, 45, 48 v1 to v6 analog input 1 to analog input 6. these are six single - ended analog inputs. in hardware mode, the analog input range on these channels is determined by the range pin. in software mode, it is determined by bit rngc to bit rnga of the co ntrol register (see table 9 ). 34, 35, 40, 41, 46, 47, 50, 60 av cc analog supply voltage, 4.75 v to 5.25 v. the av cc pin is the supply voltage for the adc cores. ideally, t he av cc and dv cc voltages are at the same potential and m ust not be more than 0.3 v apart, even on a transient basis. decouple t hese supply pins to agnd, and place 10 f and 100 nf decoupling capacitors on the av cc pins. 51 refin/refout reference input/ reference output. the on - chip reference is available on p in 51 for external use to the ad7656a . alternatively, the internal reference can be disabled and an external reference can be applied to this input. see the reference sectio n . when the internal reference is enabled, decouple p in 51 using at least a 10 f decoupling capacitor. 54, 56, 58 refcapa, refcapb, refcapc reference capacitor a, reference capacitor b, and reference capacitor c. decoupling capacitors are connected to these pins , which decouples the reference buffer for each adc pair. decouple e ach refcap x pin to agnd using 10 f and 100 nf capacitors. 61 ser/ par /sel serial/ parallel selection input. when this pin is low, the paralle l interface is selected. when this pin is high, the serial interface mode is selected. in serial mode, db10 to db 8 take on their dout c to dout a function, db0 to db 2 take on their dout select function, and db7 takes on its dcen function. in serial mode, t ie db15 and db13 to db 11 to dgnd 62 h /s sel hardware /software select input. logic input. when h /s sel = 0, the ad7656a operate s in hardware s elect mode, and the adc pairs to be simultaneously sampled are selected by the convst x pins. when h /s sel = 1, the adc pairs to be sampled simultaneously are selected by writing to the control register. in serial mode, convst a is used t o initiate conversions on the selected adc pairs. 63 wr /ref en/ dis write data/reference enable/ disable . when h /s sel pin is high and both cs and wr are logic low, db15 to db 8 are used to write data to the internal control register. when the h /s sel pin is low, this p in is used to enable or disable the internal reference. when h /s sel = 0 and ref en/ dis = 0, the internal reference is disabled , and an external reference must be applied to the refin/refout pin. when h /s sel = 0 and ref en/ dis = 1, the internal reference is enabled and the refin/refout pin must be deco upled. see the reference section . 1 multifunction pin names may be referenced by their relevant function only. rev. 0 | page 9 of 28
ad7656a data sheet typical performance characteristics 0 ?160 0 frequency (khz) (db) 125 11 127-004 ?20 ?40 ?60 ?80 ?100 ?120 ?140 25 50 75 100 v dd /v ss = 15v av cc /dv cc /v drive = +5v internal reference 10v range t a = 25c f s = 250ksps f in = 50khz snr = +87.33db sinad = +87.251db thd = ?104.32db sfdr = ?104.13db figure 4 . fft for 10 v range 0 ?160 0 frequency (khz) (db) 125 11 127-005 ?20 ?40 ?60 ?80 ?100 ?120 ?140 25 50 75 100 v dd /v ss = 12v av cc /dv cc /v drive = +5v internal reference 5v range t a = 25c f s = 250ksps f in = 50khz snr = +86.252db sinad = +86.196db thd = ?105.11db sfdr = ?98.189db figure 5 . fft for 5 v range 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 11 127-006 code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range inl wcp = 0.64lsb inl wcn = ?0.76lsb figure 6 . typical inl 2.0 ?2.0 0 10k 20k 30k 40k 50k 60k 65535 11 127-007 code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps 2 v ref range dnl wcp = 0.81lsb dnl wcn = ?0.57lsb figure 7 . typical dnl 90 60 10 1000 11127-012 analog input frequency (khz) sinad (db) 100 85 80 75 70 65 av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v 10v range av cc /dv cc / v drive = +5v v dd /v ss = 12v 5v range av cc /dv cc / v drive = +5v v dd /v ss = 5.25v 5v range av cc /dv cc / v drive = +4.75 v v dd /v ss = 10v 10v range f sample = 250ksps internal reference t a = 25c figure 8 . sinad vs. analog input frequency ?60 ?120 10 1000 11 127-013 analog input frequency (khz) thd (db) 100 ?70 ?80 ?90 ?100 ?110 av cc /dv cc / v drive = +5v v dd /v ss = 12v 5v range av cc /dv cc / v drive = +5.25v v dd /v ss = 16.5v 10v range f sample = 250ksps internal reference t a = 25c av cc /dv cc /v drive = +5v v dd /v ss = 5.25v 5v range av cc /dv cc / v drive = +4.75v v dd /v ss = 10v 10v range figure 9 . thd vs. analog input frequency rev. 0 | page 10 of 28
data sheet ad7656a ?60 ?120 10 100 11 127-014 analog input frequency (khz) thd (db) ?70 ?80 ?90 ?100 ?110 v dd /v ss = 16.5v av cc /dv cc /v drive = +5.25v t a = 25c internal reference 4 v ref range r source = 1000? r source = 10? r source = 100? r source = 50? r source = 220? figure 10 . thd vs. analog input frequency for various source impedances, 4 v ref range ?40 ?120 10 100 11 127-015 analog input frequency (khz) thd (db) ?50 ?60 ?70 ?80 ?90 ?100 ?110 v dd /v ss = 12v av cc /dv cc /v drive = +5v t a = 25c internal reference 2 v ref range r source = 1000? r source = 100? r source = 50? r source = 220? r source = 10? ?55 125 11 127-016 temperature (c) reference voltage (v) ?35 ?15 5 25 45 65 85 105 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 av cc /dv cc /v drive = +5v v dd /v ss = 12v figure 12 . reference voltage vs. t emperature 3.20 2.70 ?55 125 11 127-017 temperature (c) conversion time (s) 3.15 3.10 3.05 3.00 2.95 2.90 2.85 2.80 2.75 ?35 ?15 5 25 45 65 85 105 av cc /dv cc /v drive = +5v v dd /v ss = 12v figure 13 . conversion time vs. temperature 3500 ?5 code number of occurrences 3 3000 2500 2000 1500 1000 500 ?4 ?3 ?2 ?1 0 1 2 v dd /v ss = 15v av cc /dv cc /v drive = +5v internal reference 8192 samples 11 127-018 25 168 1532 3212 2806 392 57 0 0 0 figure 14 . histogram of codes 100 40 30 530 11 127-019 supply ripple frequency (khz) psrr (db) 90 80 70 60 50 80 130 180 230 280 330 380 430 480 v dd v ss f sample = 250ksps 2 v ref range internal reference t a = 25c f in = 10khz 100nf on v dd and v ss figure 15 . psrr vs. supply ripple frequency rev. 0 | page 11 of 28
ad7656a data sheet ?40 140 11 127-020 temperature (c) snr (db) ?20 0 20 40 60 80 100 120 83.0 83.5 84.0 84.5 85.0 85.5 86.0 86.5 87.0 5v range av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps f in = 50khz internal reference 10v range av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v figure 16 . snr vs. temperature ?100 ?107 ?40 140 11 127-021 temperature (c) thd (db) ?101 ?102 ?103 ?104 ?105 ?106 ?20 0 20 40 60 80 100 120 10v range av cc /dv cc /v drive = +5.25v v dd /v ss = 16.5v 5v range av cc /dv cc /v drive = +5v v dd /v ss = 12v f sample = 250ksps f in = 50khz internal reference figure 17 . thd vs. temperature 120 60 0 11 127-022 frequency of input noise (khz) channel-to-channel isolation (db) av cc /dv cc /v drive = 5v v dd /v ss = 12v t a = 25c internal reference 2 v ref range 30khz on selected channel 110 100 90 80 70 20 40 60 80 100 120 140 figure 18 . channel - to - channel isolation 30 0 ?40 100 11 127-023 temperature (c) dynamic current (ma) 25 20 15 10 5 ?20 0 20 40 60 80 10v range 5v range av cc /dv cc /v drive = +5v f sample = 250ksps for 5v range v dd /v ss = 12v for 10v range v dd /v ss = 16.5v figure 19 . dynamic current vs. temperature rev. 0 | page 12 of 28
data sheet ad7656a terminology integral n onlinearity (inl) inl is t he maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a ? lsb below the first code transition and full scale at ? lsb above the last code transition. differential nonlinearity (dnl) dnl is t he difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero - scale error the bipolar zero - scale error is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, that is, agnd ? 1 lsb. bipolar zero - scale error matching the bipolar zero - scale error matching is the difference in bipolar zero - code error between any two input channels. positive full - scale error the positive full - scale error is the deviatio n of the last code transition (011 110) to (011 111) from the ideal (4 v ref C 1 lsb or 2 v ref ? 1 lsb) after adjusting for the bipolar zero scale error. positive full - scale error matching the positive full - scale error matching is the difference in positive full - scale error between any two input channels. negative full - scale error the negative full - scale error is the deviation of the first code transition (10 000) to (10 001) from the ideal (?4 v ref + 1 lsb or ?2 v ref + 1 lsb) after adjustin g for the bipolar zero - code error. negative full - scale error matching the negative full - scale error matching is the difference in negative full - scale error between any two input channels. track - and - hold acquisition time the track - and - hold amplifier return s to track mode at the end of the conversion. the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1 lsb, after the end of the conversion. see the track - and - hold amplifiers section for more details. signal -to - noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. signal -to - noise - and - distortion (sinad) ratio the sinad ratio is the measured ratio of signal - to - noise - and - distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signa ls up to half the sampling frequency ( f s ample /2, excluding dc). the ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n - bit convert er with a sine wave input is given by sinad = (6.02 n + 1.76) db th erefore , sinad is 98 db for a 16 - bit converter. total harmonic distortion (thd) thd is th e ratio of the rms sum of the harmonics to the fundamental. for the ad7656a , it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) db ( v v v v v v thd + + + + = v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise the pea k harmonic or spurious noise is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s ample /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinea rities create distortion products at sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n are equal to 0. for exampl e, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7656a is tested using the ccif standard in wh ich two input frequencies near the maximum input bandwidth are used. in this case, the second - order terms are usually distanced in frequency from the original sine waves, and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - and third - order terms are specified separately. the calculation of the intermodulation distortion is per the thd specification , where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. rev. 0 | page 13 of 28
ad7656a data sheet channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full - scale, 100 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 30 khz signal. power supply rejection ratio (psr r ) variations in power supply affect the full - scale transition but not the linearity of the converter . power supply rejection is the maximum change in the full - scale transition point due to a change in power supply voltage from the nominal value. see the typical performance characteristics section. figure 15 shows the power supply rejection ratio vs. supply ripple frequency for the ad7656a . the power supply rejection ratio is defined as the ratio of the power in the adc output at the full - s cale f requency , f , to the power of a 200 mv p - p sine wave applied to the v dd and v ss supplies of the f s ample of the adc . psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc output. pf s is equa l to the power at frequency f s coupled onto the v dd and v ss supplies. percent full - scale ratio ( % fsr ) %fsr is calculated using the full theoretical span of the adc. rev. 0 | page 14 of 28
data sheet ad7656a theory of operation converter details the ad7656a is a high speed, low power converter that allow s the simultaneous sampling of six on - chip analog - to - digital converts ( adcs ) . the analog inputs on the ad7656a can accept tru e bipolar input signals. the range pin/rng x bits are used to select either 4 v ref or 2 v ref as the input range for the next conversion. the ad7656a contains six successive approximation ( sa r ) adcs, six track - and - hold amplifiers, an on - chip 2.5 v reference , reference buffers, and high speed parallel and serial interfaces. the ad7656a allow s the simultaneous sampling of all six adcs w hen the three convst x pins (convst a, convst b, and convst c) are tied together. alternatively , the six adcs can be grouped into three pairs. each pair has an associated convst signal used to initiate simultaneous sampling on each adc pair, on four adcs, or on all six adcs. convst a is used to initiate simultaneous sampling on v1 and v2, convst b is used to initiate simultaneous sampling on v3 and v4, and convst c is used to initiate simultaneous sampling on v5 and v6. a conversion is initiated on the ad7656a by pulsing the convst x input. on the rising edge of convst x, the track - and - hold amplifier of the selected adc pair is placed into hold mode and the conversions are started. after the rising edge of convst x, the busy signal goes high to indicate that the conversion is taking place. the conversion clock for the ad7656a is internally generated, and the conversion time for the device i s 3 s. the busy signal returns low to indicate the end of conversion. on the falling edge of busy, the track - and - hold amplifier returns to track mode. data can be read from the output register via the parallel or serial interface. track - and - hold amplifier s the track - and - hold amplifiers on the ad7656a allow the adcs to accurately convert an input sine wave of full - scale amplitude to 16 - bit resolution. the input bandwidth of the track - and - hold ampli fiers is greater than the nyquist rate of the adc, even when the ad7656a is operating at its maximum throughput rate. the device can handle input frequencies of up to 12 mhz. the track - and - hold am plifiers sample their respective inputs simultaneously on the rising edge of convst x. the aperture time (that is, the delay time between the external convst x signal actually entering hold) for the track - and - hold is 10 ns. this is well matched across all six track - and - hold amplifiers on one device and from device to device. this allows more than six adcs to be sampled simultaneously. the end of the conversion is signaled by the falling edge of busy, and it is at this point that the track - and - hold amplifier s return to track mode and the acquisition time begins. analog input the ad7656a can handle true bipolar input voltages. the logic level on the range pin or the value written to the rngx bits in the control register determines the analog input range on the ad7656a for the next conversion. when the range pin or rngx bit is 1, the analog input range for the next conversion is 2 v ref . when the range pin or rngx bit is 0, the analog input range for the next conversion is 4 v ref . d1 d2 v dd v dd _interna l c2 r1 v1 v ss v ss _interna l c1 11127-024 figure 20 . equivalent analog input structure figure 20 shows an equivalent circuit of the analog input of structure of the ad7656a . the two diodes , d1 and d2, provide esd protection for the analog inputs. c are must be taken to ensure that the analog input signal never exceeds the v dd and v ss supply r ail limits by more than v ss + 1 v and v dd ? 1 v. signals exceeding this value cause these diode to become forward - biased and to start conducting into the substrate. the maximum current these diodes can conduct without causing irreversible damage to the dev ice is 10 ma. capacitor c1 in figure 20 is typically about 4 pf and can be attributed primarily to pin capacitance. resistor r1 is a lumped component made up of the on resistance of a switch ( that is, track - and - hold switch). th is resistor is typically about 25 ?. capacitor c2 is the adc sampling capacitor and has a capacitance of 10 pf typically. the ad7656a require s v dd and v ss dual supplies for the high voltage analog input structures. thes e supplies must be greater than the analog input range (see table 6 for the requirements on these supplies for each analog input range). the ad7656a require s a low volta ge av cc supply of 4.75 v to 5.25 v to power the a dc core, a dv cc supply of 4.75 v to 5.25 v for the digital power, and a v drive supply of 2.7 v to 5.25 v for the interface power. to meet the specified performance when using the minimum supply voltage for the selected analog input range, it may be necessary to reduce the throughput rate from the maximum throughput rate. table 6 . minimum v dd /v ss supply voltage requirements analog input range (v) reference voltage (v) full - scale input (v) minimum v dd /v ss (v) 4 v ref 2.5 10 11 4 v ref 3.0 12 13 2 v ref 2.5 5 6 2 v ref 3.0 6 7 rev. 0 | page 15 of 28
ad7656a data sheet adc transfer functio n the output coding of the ad7656a is twos complement. the desi gned code transitions occur midway between successive integer lsb values, that is, 1/2 lsb and 3/2 lsb. the lsb size is fsr/65 , 536 for the ad7656a . the ideal transfer characteristic is shown in figure 21. 01 1... 11 1 01 1... 1 10 000...001 000...000 11 1... 11 1 ?fsr/2 + 1/2lsb +fsr/2 ? 3/2lsb agnd ? 1lsb analog input adc code 100...010 100...001 100...000 11127-025 figure 21 . transfer characteristic the lsb size is dependent on the analog input range selected (see table 7 ). table 7 . lsb size for each analo g input range input range (v) lsb size (mv) full scale range 10 0.305 20 v/65 , 536 5 0.152 10 v/65 , 536 reference section either t he r e fin/refout pin allows access to the 2.5 v reference of the ad7656a , or it allows an external reference to be connected , providing the reference source for the conversions of the device . the ad7656a can accommodate a 2.5 v to 3 v external reference ra nge. when using an external reference, the internal reference must be disabled. after a reset, the ad7656a default s to operating in external reference mode with the internal reference buffers enab led. the internal reference can be enabled in either hardware or software mode. to enable the internal reference in hardware mode, set the h /s sel pin to 0 and the ref en/ dis pin to 1. to enable the internal reference in software mode, set the h /s sel pin to 1 and write to the control register to set db9 of the control register to 1. for the internal reference mode, decouple the refin/refout pin using 10 f and 100 nf capacitors. the ad7656a contain s three on - chip reference buffers. each of the three adc pairs has an associated reference buffer. these reference buffers require external decoupling capacitors on the refcapa, refcapb, and refcapc pin s.p lace 10 f and 100 nf decoupling capacitors on these refcap x pins. the internal reference buffers can be disabled in software mode by writing to bit db8 in the internal control register. if the serial interface is selected , the internal reference buffer s can be disabled in hardware mode by setting the db14/refbuf en /dis pin high. if the internal reference and its buffers are disabled, apply an external buffered reference to the refcap x pins. typical connection d iagram figure 22 shows the typical connection diagram for the ad7656a . there are eight avcc supply pins on the device . the avcc supply is the supply that is used for the ad7656a conversion process; therefore, it must be well decoupled. individually decouple e ach av cc supply pin with a 10 f tantalum capacitor and a 100 nf ceramic capacitor. the ad7656a can operate with the internal reference or an externally applied reference. in this configuration , the device is configured to operate with the external reference. the refin/refout pin is decoupled with a 10 f and 100 nf capacitor pair. the three internal reference buffers are enabled. each of the refcap x pins is decoupled with the 10 f and 100 nf capacitor pair. + 100nf 100nf + + dv cc 100nf + 100nf dv cc av cc agnd dgnd v drive dgnd v dd agnd + 100nf v s s agnd + 100nf + 100nf refcapa, refcapb, refcapc agnd refin/refout agnd db0 to db15 convst a, convst b, convst c cs rd busy ser/par/sel h/s sel w/b range reset stby v drive ad7656a 10f 10f 10f 10f 10f 10f 10f digital supply voltage +3v or +5v ana l o g supply voltage 5v 1 1 decoupling shown on the av cc pin applies to each av cc pin. 2 see the power supply sequencing section. +11.0v to +16.5v 2 supply 2.5v ref six analog inputs ?11.0v to ?16.5v 2 supply parallel microprocessor/ microcontroller/ dsp interface 11 127-122 figure 22 . typical connection diagram rev. 0 | page 16 of 28
data sheet ad7656a si x of the av cc supply pins are used as the supply to the six adc cores on the ad7656a and, as a result, are used for the conversion process. each analog input pin is surrounded by an av cc supply pin and an agnd pin. these av cc and agnd pins are the supply and ground for the individual adc cores. for example, pin 33 is v1, pin 34 is the av cc supply for adc core 1, and pin 32 is agnd for adc core 1. an alternative reduced decoupling solution is to group these six av cc supply pins into three pairs, pin 34 and pin 35, pin 40 and pin 41, and pin 46 and pin 47. for the ad7656a , a 100 f decoupling capacitor can be placed on each of the pin pairs. decouple all of the other sup ply and reference pins with a 10 f decoupling capacitor. if the same supply is being used for the av cc supply and dv cc supply, place a ferrite or small rc filter between the supply pins. the agnd pins are connected to the analog ground plane of the syst em. the dgnd pins are connected to the digital ground plane in the system. connect the agnd and dgnd planes together at one place in the system. make this connection as close as possible to the ad7 656a in the system. the v drive supply is connected to the same supply as the processor . the voltage on v drive controls the voltage value of the output logic signals. decouple the v dd and v ss signals with a minimum 10 f decoupling capacitor. these suppli es are used for the high voltage analog input structures on the ad7656a analog inputs. driving the analog i nputs together, the driver amplifier and the analog input circuit used for the ad7656a must settle for a full - scale step input to a 16- bit level (0.0015%), which is within the specified 550 ns acquisition time of the ad7656a . the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7656a . in addition, t he driver needs to have a thd perfor mance suitable for the ad7656a . the ad8021 meets all these requirements . the ad802 1 needs an external compensation capacitor of 10 pf. if a dual version of the ad8021 is required, the ad8022 can be used. the ad8610 and the ad797 can also be used to drive the ad7656a . interface section the ad7656a provides two interface options: a parallel interface and a high speed serial interface. the required interface mode is selected via the ser/ pa r sel pin. the parallel interface can operat e in word ( w /b = 0) or byte ( w /b = 1) mode. the interface modes are discussed in the following sections. parallel interface (ser/ par/ sel = 0) the ad7656a consist s of six 16 - bit adcs. a simultaneous sample of all six adcs can be performed by connecting all three convst x pins together ( convst a, convst b, and convst c) . the ad7656a need s to see a convst x pulse to initiate a conversion; this typically consist s of a falling convst x edge followed by a rising convst x edge . the rising edge of convst x initiates simultaneous conversions on the selected adcs. the ad7656a contains an on - chip oscillator that is used to perform the conversions. the conversion time, t conv ert , is 3 s. the busy signal goes low to indicate the end of conversion. the falling edge of the busy signal is used t o place the track - and - hold amplifier into track mode. the ad7656a also allow s the six adcs to be converted simultaneously in pairs by pulsing the three convst x pins independently. convst a is use d to initiate simultaneous conversions on v1 and v2, convst b is used to initiate simultaneous conversions on v3 and v4, and convst c is used to initiate simultaneous conversions on v5 and v6. the conversion results from the simultaneously sampled adcs are stored in the output data registers. data can be read from the ad7656a via the parallel data bus with standard cs and rd signals ( w /b = 0). to read the data over the parallel bus, tie ser/ pa r sel low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines , the db0 to db15 pins , lea ve their high impedance state when both cs and rd are logic low. rev. 0 | page 17 of 28
ad7656a data sheet v1 v2 v3 v4 v5 v6 convst a, convst b, convst c busy cs rd data t quiet t 7 t 8 t 9 t 4 t 2 t 3 t 5 t 6 t acq t convert 11127-027 t 10 figure 23 . parallel interface timing diagram ( w /b = 0) low byte high byte db15 to db8 cs rd t 3 t 6 t 7 t 8 t 4 t 5 t 9 11127-028 figure 24 . parallel in terface ? read cycle for byte mode of operation ( w /b = 1, hben = 0) the cs signal can be permanently tied low, and the rd signal can be used to access the conversion results. a read operation can take pl ace after the busy signal goes low. the number of required read operations depends on the number of adcs that are simultaneously sampled (see figure 23 ). if convst a and convst b are simultaneously brought low, four read opera tions are required to obtain the conversion results from v1, v2, v3, and v4. if convst a and convst c are simultaneously brought low, four read operations are required to obtain the conversion results from v1, v2, v5, and v6. the conversion results are out put in ascending order. when using the three convst x signals to independently initiate conversions on the three adc pairs, ensure that a conversion is not initiated on a channel pair when the busy signal i s high. it is also recommended not to initiate a c onversion during a read sequence because doing so can affect the performance of the con version. for the specified performance, it is recommended to perform the read after the conversion. for unused input channel pairs, tie the associated convst x pin to v d rive . if there is only an 8 - bit bus available, the ad7656a interface can be configured to operate in byte mode ( w /b = 1). in this configuration, the db7/hben/dcen pin takes on i ts hben function. each channel conversion result from the ad7656a can be accessed in two read operations, with eight bits of data provided on db15 to db8 for each of the read operations (see figure 24 ). the hben pin determines whether the read operation first accesses the high byte or the low byte of the 16- bit conversion result. to always access the low byte first on db15 to db8, tie the hben pin low. t o always access the high byte first on db15 to db8, tie the hben pin high. in byte mode when all three convst x pins are pulsed together to initiate simultaneous conversions on all six adcs, 12 read operations are necessary to read back the six 16 - bit conv ersion results. leave db6 to db 0 unconnected in byte mode. rev. 0 | page 18 of 28
data sheet ad7656a software selection o f adcs the h /s sel pin determines the source of the combination of adcs that are to be simultaneously sampled. when the h /s sel p in is logic low, the combination of channels to be simultaneously sampled is determined by the convst a, convst b, and convst c pins. when the h /s sel pin is logic high, the combination of channels selected for simultaneous sampling is de termined by the contents of the db15 to db13 bits in the control register . in this mode, a write to the control register is necessary. the control register is an 8 - bit write - only register. data is written to this register using the cs an d wr pins and the db15 to db 8 data pins (see figure 25 ). the control register is detailed in table 8 . to select an adc pair to be simultaneously sampled, set the corresponding data line high during the write operation. data db15 to db8 cs t 13 t 15 t 14 t 11 t 12 wr 11127-029 figure 25 . parallel interface write cycle for word mode ( w /b= 0) the ad7656a control register allows individual rang es to be programmed on each adc pair. db12 to db10 bits in the control register are used to program the range on each adc pair. after a reset occurs on the ad7656a , the control register contains a ll zeros. the convst a signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. the convst b and convst c signals can be tied low when operating in software mode ( h /s sel = 1) . the number of read pulses required depends on the number of adcs selected in the control register and on whether the devices are operating in word or byte mode. the conversion results are output in ascending order. during the write operation, data bus b it db15 to data bus bit db8 are bidirectional and become inputs to the control register when rd is logic high and cs and wr are logic low. the logic state on db15 through db8 is latched into the control register when wr goes logic high. table 8 . control register bit s (default all 0s) db15 db14 db13 db12 db11 db10 db9 db8 vc vb va rngc rngb rnga refen refbuf table 9 . control register bi t function descriptions (default all 0s) bit mnemonic description db15 vc this bit select s the v5 and v6 analog inputs for the next conversion. when this bit is set to 1, v5 and v6 are simultaneously converted on the next convst a rising edge. db14 vb th is bit select s the v3 and v4 analog inputs for the next conversion. when this bit is set to 1, v3 and v4 are simultaneously converted on the next convst b rising edge. db13 va this bit select s the v1 and v2 analog inputs for the next conversion. when thi s bit is set to 1, v1 and v2 are simultaneously converted on the next convst c rising edge. db12 rngc this bit select s the analog input range for the v5 and v6 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next convers ion. when this bit is set to 0, the 4 v ref range is selected for the next conversion. db11 rngb this bit select s the analog input range for the v3 and v4 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next conversion . when this bit is set to 0, the 4 v ref rang e is selected for the next conversion. db10 rnga this bit select s the analog input range for the v1 and v2 analog inputs . when this bit is set to 1, the 2 v ref range is selected for the next conversion. wh en this bit is set to 0, the 4 v ref rang e is selected for the next conversion. db9 refen this bit select s the internal reference or an external reference. when this bit is set to 0, the external reference mode is selected. when this bit is set to 1, th e internal reference is selected. db8 refbuf this bit select s between using the internal reference buffers and choosing to bypass these reference buffers. when this bit is set to 0, the internal reference buffers are enabled and decoupling is required on the refcap x pins. when this bit is set to 1, the internal reference buffers are disabled and a buffered reference is applied to the refcap x pins. rev. 0 | page 19 of 28
ad7656a data sheet changing the analog input range ( h /s sel = 0) the ad7656a range pin allows the user to select either 2 v ref or 4 v ref as the analog input range for the six analog inputs. when the h /s sel pin is low, the logic state of the range pin is sampled on the falli ng edge of the busy signal to determine the range for the next simultaneous conversion. when the range pin is logic high at the falling edge of the busy signal, the range for the next conversion is 2 v ref . when the range pin is logic low at the falling edge of the busy signal, the range for the next conversion is 4 v ref . after a reset pulse, the range is updated on the first falling busy edge after the reset pulse. changing the analog input range ( h /s sel = 1) when the h /s sel pin is high, the range can be changed by writing to the control register. bits[ db12: db 10] in the control register are used to select the analog input ranges for the next conversion. each analog input pair has an associated range bit, allowing independent ranges to be programmed on each adc pair. when the rngx bit is set to 1, the range for the next conversion is 2 v ref . when the rngx bit is set to 0, the range for the next conversion is 4 v ref . serial interface (ser/ par / sel = 1) by pulsing one, two, or all three convst x signals, the ad7656a use their on - chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of convst x. after the rising edge of convst x, the busy signal goes high to indicate that the conversion has started. it returns low when the conversion is complete 3 s later. the output register is loaded with the new conversion results, and data can be read from th e ad7656a . to read the data back from the device over the serial interface, tie ser/ pa r high. the cs and sclk signals are used to transfer data from the ad7656a . the device has three dout x pins : dout a, dout b, and dout c. data can be read back from the device using one, two, or all three dout x lines. figure 26 shows six si multaneous conversions and the read sequence using three dout x lines. also in figure 26 , 32 sclk transfers are used to access data from the ad7656a ; however, two 16 sc lk individually framed transfers with the cs signal can also be used to access the data on the three dout x lines. when the serial interface is selected and the conversion data clock s out on all three dout x lines, tie db0/sel a, db1/sel b , and db2/sel c to v drive . these pins are used to enable the dout a to dout c lines, respectively. if it is required to clock conversion data out on two data out lines, use dout a and dout b. to enable dout a and dout b, tie db0/sel a and db1/sel b to v dri ve and tie db2/sel c low. when six simultaneous conversions are performed and only two dout x lines are used, a 48 sclk transfer can be used to access the data from the ad7656a . the read sequence is shown in figure 27 for a simultaneous conversion on all six adcs using two dout x lines. if a simultaneous conversion occurred on all six adcs, only two dout x lines are used to read the results from the ad7656a . dout a clocks out the result from v1, v2, and v5, and dout b clocks out the results from v3, v4, and v6. data can also be clocked out using just one dout x line, in which case, use dout a to access the conve rsion data. to configure the ad7656a to operate in this mode, tie db0/sel a to v drive and tie db1/sel b and db2/sel c low. the disadvantage of using only one dout x line is that the throughput rat e is reduced. data can be accessed from the ad7656a using one 96 - sclk transfer, three 32 - sclk individually framed transfers, or six 16 - sclk individually framed transfers. in serial mode, tie the rd signal low. leave t he unused dout x line(s) unconnected in serial mode. v1 v2 convst a, convst b, convst c busy cs dout a dout b dout c 32 v3 v4 v5 v6 sclk 16 t quiet t acq t convert 11127-030 figure 26 . serial interface with three dout x lines rev. 0 | page 20 of 28
data sheet ad7656a v1 v2 v5 dout a dout b 48 v3 v4 v6 sclk cs 11127-031 figure 27 . serial interface with two dout x lines busy acquisition conversion acquisition sclk cs dout a, dout b, dout c db15 db14 db13 db1 db0 t acq t 10 t convert t 2 t 1 t quiet t 21 t 20 t 17 t 16 t 18 t 19 11127-032 convst a, convst b, convst c f igure 28 . serial read operation digital host convert cs sclk ad7656a ad7656a convst x convst x cs cs sclk sclk data in1 data in2 dout a dout b dout a dout b dcin a dcin b dcen = 1 device 1 dcen = 0 device 2 11127-033 figure 29 . daisy - chain configuration serial read operatio n figure 28 shows the timing diagram for reading data from the ad7656a serial interface . the sclk input signal provides the clock source for the serial interface. the cs signal goes low to access data from the ad7656a . the falling edge of cs takes the bus out of a three - state condition and clocks out the msb of the 16 - bit conversion result. the adcs output 16 bits for each conversion result; the data stream of the ad7656a consists of 16 bits of conversion data provided msb first. the first bit of the conversion result is valid on the first sclk falling edge after the cs falling edge. the subse quent 15 data bits are clocked out on the rising edge of the sclk signal. data is valid on the sclk falling edge. to access each conversion result, provide 16 clock pulses to the ad7656a . figure 28 shows how a 16- sclk read is used to access the conversion results. daisy - chain mode (dcen = 1 , ser/ par / sel = 1) when reading conversion data back from the ad7656a using their three, two, and one dout x pins, it is possible to configure the device to operate in daisy - chain mode using the dcen pin. this daisy - chain feature allows multiple ad7656 a devices to be cascaded together and is useful for reducing the component count and wiring connections. an example connection of two devices is shown in figure 29 . this configuration shows the use of two dout x lines. simultaneo us sampling of the 12 analog inputs is possible by using a common convst x signal. the db5, db4, and db3 pins are used as the dcin a to dcin c data i nput pins for the daisy - chain mode. rev. 0 | page 21 of 28
ad7656a data sheet the rising edge of convst x is used to initiate a conversion on the ad7656a . after the busy signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. figure 30 shows the ser ial timing diagram when operating two ad7656a devices in daisy - chain mode. the cs falling edge is used to frame the serial transfer from the ad7656a to take the bus out of three - state and to clock out the msb of the first conversion result. in the example shown in figure 30 , all 12 adc channels are simultaneously sampled. two d out x lines are used to read the conversion results in this example. cs frames a 96 - sclk transfer. during the first 48 sclks, the conversion data is transferred from device 2 to device 1. dout a on device 2 transfers conversion data from v1, v2, and v5 into dcin a in device 1. dout b on device 2 transfers conversion results from v3, v4, and v6 to dcin b in device 1. during the first 48 sclks, device 1 transfers data into the digital host. dout a on device 1 transfers conversion data from v1, v2, and v5. dout b on device 1 transfers conversion data from v3, v4, and v6. during the last 48 - sclks, device 2 clocks out zeros and device 1 shifts the data clocked in from device 2 during the first 48 sclks into the digital host. this example can al so be implemented using six 16 - sclk individually framed transfers if dcen remains high during the transfers. figure 31 shows the timing if two ad7656a devices are configured in daisy - chain mode and are operating with three dout x lines. assuming a simultaneous sampling of all 12 inputs occurs, the cs frames a 64 - sclk transfer during the read operation. during the first 32 sclks of this transfer, the conversion results from device 1 are clocked into the digital host , and the conversion results from device 2 are clocked into device 1. during the last 32 sclks of the transfer, the conversion results from device 2 are clocked out of device 1 and into the digital host. device 2 clocks out zeros. device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 msb v1 lsb v1 msb v2 lsb v5 msb v1 lsb v1 msb v2 lsb v2 msb v5 lsb v5 1 2 3 busy sclk cs 15 16 17 31 32 33 47 48 49 63 65 64 94 95 96 device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 msb v3 lsb v3 msb v4 lsb v6 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 msb v6 lsb v6 device 2, dout b 11127-034 convst a, convst b, convst c figure 30 . daisy - chain serial interface timing with two dout x lines device 1, dout a msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 msb v1 lsb v1 msb v2 lsb v2 1 2 3 busy sclk cs 15 16 17 31 32 33 47 48 49 63 64 device 2, dout a msb v3 lsb v3 msb v4 lsb v4 device 2, dout b device 1, dout b msb v3 lsb v3 msb v4 lsb v4 msb v3 lsb v3 msb v4 lsb v4 device 1, dout c msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 msb v5 lsb v5 msb v6 lsb v6 device 2, dout c 11127-035 convst a, convst b, convst c figure 31 . daisy - chain serial interface timing with three dout x lines rev. 0 | page 22 of 28
data sheet ad7656a s tandby/partial power - down modes of operation (ser/par / sel = 0 or ser/par / sel = 1) each adc pair can be individually placed into partial power - down mode by bringing the convst x signal low before the falling edge of busy. b ring the convst x signal high to p ower up the adc pair and place the track - and - hold amplifier into track mode. after the power - up time from the partial power - down has elapsed, the convst x signal typically receive s a rising edge to initiate a valid conversion. in partial power - down mode, t he reference buffers remain powered up. while an adc pair is in partial power - down mode, conversions can still occur on the other adcs. the ad7656a has a power - down mode whereby the device can be placed int o a low power mode consuming 100 mw maximum . the ad7656a is placed into standby mode by bringing the logic input stby low and can be powered up again for normal operat ion by bringing stby logic high. the output data buffers are still operational when the ad7656a is in standby mode, meaning the user can continue to access the conversion results of the device . this standby feature can be used to reduce the average power consumed by the ad7656a when operating at lower throughput rates. the ad7656a can be placed into standby at the end of each conversion when busy goes low and taken out of standby again prior to the next conversion. the wake - up time is when the ad7656a com e s out of standby mode . the wake - up time limits the maximum throughput rate at which the ad7656a can operate when powering down between conversions. see the specifications section. rev. 0 | page 23 of 28
ad7656a data sheet application hints layout design t he printed circuit board (pcb) that houses the ad7656a so that the analog and digital sections are separated and confined to different areas of the board. use a t least one groun d plane. the ground plane c an be common or split between the digital and analog sections. in the case of the split plane, join the digital and analog ground planes in only one place, preferably underneath the ad7656a , or at least as close as possible to the device . if the ad7656a is in a system where multiple devices require analog - to - digital ground connections, still make the connection at only one point, a star ground point, and established it as close as possible to the ad7656a . make g ood connections to the ground plane. avoid shari ng one connection for multiple ground pins. use i ndividual vias or multiple vias to the ground plane for each ground pin. avoid running digital lines under the device because doing so couples noise onto the die. allow t h e analog ground plane to run under the ad7656a to avoid noise coupling. shield fast switching signals , like convst x or clocks , with digital ground to avoid radiating noise to other sections of the board, and ensure that they never run near the analog signal paths. avoid c rossover of digital and analog signals. run t races in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. for t he power supply lines to the av cc , dv cc , v drive , v dd , and v ss pins on the ad7656a use as large a trace as possible to provide low impedance paths and to reduce the effect of glitches on the power supply lines. establish g ood connections between the ad7656a supply pins and the power tracks on the board; involve the use of a single via or multiple vias for each supply pin. good decoupling is also important to lower the supply impe dance presented to the ad7656a and to reduce the magnitude of the supply spikes. place d ecoupling ceramic capacitors, typically 100 nf, on all of the power supply pins, v dd , v ss , av cc , dv cc , and v drive . place t hese decoupling capacitors close to, but ideally right up against, these pins and their corresponding ground pins. additionally, place low esr 10 f capacitors on each of the supply pins. avoid sharing these capacitors between pins. use big v ias to connect the capacitors to the power and ground planes. use wide, short traces between the via and the capacitor pad, or place the via adjacent to the capacitor pad to minimize parasitic inductances. recommended decoupling capacitors are 100 n f, low esr, ceramic capacitors and 10 f, l o w esr, tantalum capacitors for the av cc decoupling. place a large tantalum decoupling capacitor where the av cc supply enters the board. an alternative reduced decoupling arrangement is outlined in the typical connection diagram section. this decoupling arrangement groups the av cc supply pins into pairs and allows the decoupling capacitors to be shared between the supply pairs. group the six av cc core supply pins into three pairs, pin 34 and p in 35, pin 40 and pin 41, and pin 46 and pin 47. connect the supply pins in each pair together; their location on the ad7656a pin configuration easily facilitates this. for the ad7656a , decouple each pair with a 100 f capacitor. for this minimum decoupling configuration, decouple all other supply and reference pins with a 10 f decoupling capacitor. rev. 0 | page 24 of 28
data sheet ad7656a outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a t op view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 32 . 64 - lead low profile quad flat package [lqfp] (st - 64 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7656abstz ?40c to +85 c 64- lead low profile quad flat package [l qfp] st -64- 2 ad7656abstz -rl ?40c to +85c 64- lead low profile quad flat package [lqfp] st -64- 2 1 z = rohs compliant part. rev. 0 | page 25 of 28
ad7656a data sheet notes rev. 0 | page 26 of 2 8
data sheet ad7656a notes rev. 0 | page 27 of 28
ad7656a data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademark s are the property of their respective owners. d11127 - 0- 12/13(0) rev. 0 | page 28 of 28

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